The Peripheral Component Interconnect Special Interest Group (PCI-SIG) continues to release updated versions of Peripheral Component Interconnect Express (PCIe) that will improve the speeds at which data can move within computer systems, in particular, those with graphics and sound.
PCIe is a high-speed serial computer expansion bus standard. PCIe protocol makes it possible to expand the output capabilities of a main computer system, such as video, sound, and network connections. As Graphical Processing Unit (GPU) computing power continues to increase, the current PCIe – version 3.0 – has remained the same. The potential for the PCIe to become a bottleneck to the device has become real, in particular for 3D rendering and simulation applications. The release of PCIe version 4.0 and version 5.0 will increase speeds and throughput, removing the potential bottleneck for these applications.
Speeds and Feeds
PCIe bandwidth is defined by the number of lanes on the bus and how much data each lane can transmit. Each version of the PCIe standard has increased the bandwidth a single lane can provide. Multiply that by the number of lanes to get the max bandwidth a given bus device could support. Typical motherboard implementations of PCIe expansion slots would be x1, x4, x8, and x16 lanes.
For PCIe Gen 3.0, a single lane can support 8.0GT/s (Gigatransfers per second), which equates to 984.6 MB/s (or Megabytes per second). So, a x16 slot would support 128GT/s or 15.8GB/s. PCIe 4.0 was released in October of 2017, however support for this standard in product is still in development. The PCIe 5.0 standard is due to be released mid-2019. PCIe is set to double single lane support with each of these releases.
The increased bus speed is important for applications that utilize highly compute-intensive add-in cards which reside on the PCIe bus, specifically GPUs. With 3D rendering or simulation applications, these “add-in cards” become the main component of the computer system.
GPU technology is also used for compute-intensive applications which don’t directly drive a display as their primary output. These applications such as deep learning, or Artificial Intelligence (AI), need maximum available computing power closest to real-time as possible. GPUs are used to augment the Central Processing Unit (CPU), or become the primary computing chip in these system designs.
These next generation PCIe standards, however, provide some challenges for motherboard designs, and other designed components which are part of the PCIe bus, such as riser cards. This article from EET Asia describes the challenge of distance – the higher speed and frequency cannot travel the same distance compared to version 3.0. So manufacturers will have to weigh the benefit of speed with the cost of motherboards, chips, connectors, cables, and new mechanical designs.
Manufacturers including AMD and Nvidia are already working on products with support for PCIe Gen 4.0. AMD and Nvidia are likely to announce a future chipset at Computex 2019. EmbedTek will continue to analyze the impact PCIe versions 4.0 and 5.0 have on system designs as the new standards become ratified, released and integrated into future motherboard core chipset technology.